1. Field of the Invention
The present invention relates to a semiconductor memory device and relates to, for example, a sense amplifier for an FBC (Floating Body Cell).
2. Related Art
A sense amplifier employed in a conventional FBC-DRAM includes a current load circuit and a CMOS latch circuit connected to a pair of sense nodes. The sense amplifier including both the current load circuit and the CMOS latch circuit can advantageously ensure accurately detecting data, i.e., can be advantageously robust against irregularity in a threshold voltage among transistors that constitute the sense amplifier. However, since both the current load circuit and the CMOS latch circuit are provided, the circuit scale of the sense amplifier is disadvantageously large. The large circuit scale of the sense amplifier greatly influences the size of the entire semiconductor memory device particularly if the sense amplifier is provided per pair of bit lines.
Furthermore, such a sense amplifier needs to wait until a potential difference between the pair of sense nodes exceeds the irregularity in the threshold voltages among the transistors. Therefore, the sense amplifier has a disadvantage the data detection speed is decreased.
The current load circuit applies a through current to each memory cell via the sense nodes and the bit lines until a signal is sufficiently developed. This disadvantageously increases current consumption of the conventional sense amplifier.